Digital dividers for carrying out division of two values, generally in binary form, are implemented in various manners for a wide range of applications, such as telecommunications equipment. For example, algorithms that implement frequency lock loops and receivers in telecommunications equipment use digital dividers for division of real values. These values are often represented as quantised integer values. One such representation scheme is known as “fixed point Q15”, which provides a 16 bit presentation of real-world signal values. In Q15, 0 (zero) bits are used to present the value on the left-hand side of the decimal point, fifteen bits are used to present values on the right-hand side of the decimal point, and one bit is used for the sign (+/−). Q15 presentation assumes that real signal values are presented in range of (−1,1), and the quantised values are in steps of 1/32767 (that is, ½15). The algorithms assume that all values that require division are decimal, in the range of −1 to 1. The arithmetic operation of division takes two input values in this range, one a dividend and the other a divisor, and produces a result or quotient. The result is represented in the same Q15 format. Any other level of quantisation can be implemented, where appropriate, although Q15 is a commonly used format.
Some examples of decimal values and the equivalent Q15 value (in decimal) are shown below.
Real ValuesQ150.516384132767−1−32768
The Q15 value is then converted to a decimal value for input into the divider. Some examples of division using Q15 format are as follows:
Real ValuesQ15 Implementation0.25/0.5 = 0.58192/16284 = 162840.5/0.9 = 0.555555616284/29490 = 18204
The Q15 representation is shown in decimal for clarity, however, a divider operates with Q15 represented numbers in a binary format.
The arithmetic operation of dividing two numbers presents a considerable problem in most DSPs or more generally, embedded system implementations. Most processing units do not have an instruction set to execute division. For example, the TI 5402 DSP, does not have a direct instruction for division. Division is implemented indirectly via the special subtraction instruction. Fast division (parallel implementation) requires many logic cells/gates involving large areas of silicon. That is why the “slow” series implementation algorithms, which use few logic gates, are very popular and mostly used in industry. These are cheaper and take up less room than parallel implementations, due to the lesser number of logic gates required.
For example, in the industry, a standard approach is commonly implemented in an ALTERA™ FPGA. ALTERA™ provides several design solutions to achieve division, however, these do not produce results in Q15 precision. The parallel implementation takes around 1200 logic cells and executes in one cycle. While obviously this is time efficient, the implementation requires a lot of silicon “real estate”. The serial divider proposed by ALTERA™ takes approximately 120 logic cells and executes in 32 cycles. Both solutions present only core division operation. Further logic, comprising approximately 100-200 logic cells, is required for interfacing, sign correction, saturation and presentation in Q15. For example, the serial implementation therefore needs a minimum of 350-400 logic cells, and executes in more than 32 cycles. While using significantly fewer gates than the parallel implementation, the execution time (in cycles) is much longer.